mdComputer8

How a computer works

I started this project out of curiosity on how a computer works.
How can logic gates like AND, OR, NAND and NOR be created with nothing more than a few transistors and resistors?
How can you make memory with these logic gates? Do calculations? Control the flow?

It didn't take long to find the excellent YouTube series of Ben Eater in which he explains all this while building a minimalistic computer on a breadboard. This inspired me to build one myself.

After building elementary logic purely based on a few discrete components, I decided just like Ben Eater to build the computer with TI 7400 Logic IC Series from the 70's to save time and space.
Where he used 74LSxx, I went for 74HCxx which are more or less equivalent but much easier to find and consume much less power (<250mA compared to >1A for the whole computer)
Also, I choose not to use breadboards because of price and difficulty to store away without disassembling it.

The final goal for the computer should be to enter a program like calculating prime-numbers in memory and run that successful. To do that Ben Eaters 16 byte memory and 16 instruction computer would not be enough. My target specification are:

- 256 bytes of RAM (8 bit addressing)
- 100+ operation instructions (1 byte operation plus optional byte for operand)
- 4 registers of which one has a decimal/hexadecimal display
- Manual input for programming/listing
- Serial input/output for autoload and terminal programming/listing

To achieve that I used some of James Bates improvements on Ben Eaters design together with some ideas of myself.

Instruction Set

Opcode	Mnemonic	Description
00	NOP	Do nothing
1A	MOV A,[adr]/var	Load value in address/variable into A
1B	MOV B,[adr]/var	Load value in address/variable into B
1D	MOV D,[adr]/var	Load value in address/variable into D
1E	MOV OUT, [adr]/var	Load value in address/variable into OUPUT
2A	MOV A, val/xxH/'C' LEA A, var/label	Load value immediate into A Load variable address into A
2B	MOV B, val LEA B, var/label	Load value immediate into B Load variable address into B
2D	MOV D, val LEA D, var/label	Load value immediate into D Load variable address into D
2E	MOV OUT, val LEA OUT, var/label	Load value immediate into OUTPUT Load variable address into OUTPUT
30	MOV A, B	Load B into A
31	MOV A, PC	Load PC into A
32	MOV A, D	Load D into A
33	MOV A, OUT	Load OUTPUT into A
34	MOV B, A	Load A into B
35	MOV B, PC	Load PC into B
36	MOV B, D	Load D into B
37	MOV B, OUT	Load OUTPUT into B
38	MOV D, A	Load A into D
39	MOV D, B	Load B into D
3A	MOV D, PC	Load PC into D
3B	MOV D, OUT	Load OUTPUT into D
3C	MOV OUT, A	Load A into OUTPUT
3D	MOV OUT, B	Load B into OUTPUT
3E	MOV OUT, PC	Load PC into OUTPUT
3F	MOV OUT, D	Load D into OUTPUT
40	MOV A, IN	Load IN into A
41	MOV B, IN	Load IN into B
42	MOV D, IN	Load IN into D
43	MOV OUT, IN	Load IN into OUT
4A	MOV [adr], A	Store A in address/variable
4B	MOV [adr], B	Store B in address/variable
4C	MOV [adr], PC	Store PC in address/variable
4D	MOV [adr], D	Store D in address/variable
4E	MOV [adr], OUT	Store OUTPUT in address/variable
4F	MOV [adr], IN	Store IN in address/variable
50	ADD A, [adr]/var	Load value in address/variable into B, A PLUS B to A, FLAGS set
51	ADD A, val	Load value immediately into B, A PLUS B to A, FLAGS set
52	ADC A, [adr]	Load value in address/variable into B, A PLUS B +CARRY to A, FLAGS set
53	ADC A, val	Load value immediately into B, A PLUS B +CARRY to A, FLAGS set
54	AND A, [adr]	Load value in address/variable into B, A AND B to A
55	AND A, val	Load value immediately into B, A AND B to A
56	INC A	Increment A
5B	ADD A, B	A PLUS B to A, FLAGS set
5C	ADD A, PC	Load PC to B, A PLUS B to A, FLAGS set
5D	ADD A, D	Load D to B, A PLUS B to A, FLAGS set
5E	ADD A, OUT	Load OUT to B, A PLUS B to A, FLAGS set
5F	ADD A, IN	Load IN to B, A PLUS B to A, FLAGS set
60	SUB A, [adr]	Load value in address/variable into B, A MINUS B to A, FLAGS set
61	SUB A, val	Load value immediately into B, A MINUS B to A, FLAGS set
62	SBB A, [adr]	Load value in address/variable into B, A MINUS B +CARRY to A, FLAGS set
63	SBB A, val	Load value immediately into B, A MINUS B +CARRY to A, FLAGS set
64	OR A, [adr]	Load value in address/variable into B, A OR B to A
65	OR A, val	Load value immediately into B, A OR B to A
66	DEC A	Decrement A
6B	SUB A, B	A MINUS B to A, FLAGS set
6C	SUB A, PC	Load PC to B, A MINUS B to A, FLAGS set
6D	SUB A, D	Load D to B, A MINUS B to A, FLAGS set
6E	SUB A, OUT	Load OUT to B, A MINUS B to A, FLAGS set
6F	SUB A, IN	Load IN to B, A MINUS B to A, FLAGS set
70	CMP A, [adr]	Load value in address/variable into B, A MINUS B, FLAGS set
71	CMP A, val	Load value immediately into B, A MINUS B, FLAGS set
72	CMB A, [adr]	Load value in address/variable into B, A MINUS B +CARRY, FLAGS set
73	CMB A, val	Load value immediately into B, A MINUS B +CARRY to A, FLAGS set
74	XOR A, [adr]	Load value in address/variable into B, A XOR B to A
75	XOR A, val	Load value immediately into B, A XOR B to A
76	NOT A	NOT A
7B	CMP A, B	A MINUS B, FLAGS set
7C	CMP A, PC	Load PC to B, A MINUS B, FLAGS set
7D	CMP A, D	Load D to B, A MINUS B, FLAGS set
7E	CMP A, OUT	Load OUT to B, A MINUS B, FLAGS set
7F	CMP A, IN	Load IN to B, A MINUS B, FLAGS set
90	JZ [adr]/label	Jump (PC) to address if ZF is set
91	JC [adr]/label	Jump (PC) to address if CF is set
92	JNZ [adr]/label	Jump (PC) to address if ZF is not set
93	JNC [adr]/label	Jump (PC) to address if CF is not set
98	JMP [[ptr]]/[var]	Jump (PC) to address in ptr/variable
99	JMP [adr]/label	Jump (PC) to address
9A	JMP A	Jump (PC) to address in A
9B	JMP B	Jump (PC) to address in B
9D	JMP D	Jump (PC) to address in D
9E	JMP OUT	Jump (PC) to address in OUTPUT
9F	JMP IN	Jump (PC) to address in IN
AA	MOV A, [[ptr]]/[var]	Load value in address in ptr/variable into A
AB	MOV B, [[ptr]]/[var]	Load value in address in ptr/variable into B
AD	MOV D, [[ptr]]/[var]	Load value in address in ptr/variable into D
AE	MOV OUT, [[ptr]]/[var]	Load value in address in ptr/variable into OUTPUT
BA	MOV [[ptr]]/[var], A	Store A in address in ptr/variable
BB	MOV [[ptr]]/[var], B	Store B in address in ptr/variable
BC	MOV [[ptr]]/[var], PC	Store PC in address in ptr/variable
BD	MOV [[ptr]]/[var], D	Store D in address in ptr/variable
BE	MOV [[ptr]]/[var], OUT	Store OUTPUT in address in ptr/variable
BF	MOV [[ptr]]/[var], IN	Store IN in address in ptr/variable
E0	OUT [adr]/var	Load value in address/variable into OUPUT
E1	OUT val	Load value immediate into OUTPUT
EA	OUT A	Load A into OUTPUT
EB	OUT B	Load B into OUTPUT
EC	OUT PC	Load PC into OUTPUT
ED	OUT D	Load D into OUTPUT
EF	OUT IN	Load IN into OUTPUT
FC	LST	Set LIST-mode PC to MAR/OUTPUT, RAM to OUTPUT)
FE	PRG	Set PROGRAM-mode PC to MAR/OUTPUT, BUS to RAM/OUTPUT)
FF	END	Halt clock